Using Compiler Technology to Drive Advanced Microprocessors

Recent years have seen the introduction of a series of ever faster, ever more complex microprocessors. These advanced microprocessors have found widespread application in machines that range from personal computers to engineering workstations to massively parallel multicomputers. Unfortunately, many of the features used to endow these processors with high peak performance numbers are diicult for either human programmers or compilers to manage. This paper looks at broad trends in microprocessor architecture, relates them back to the basic problems that they present to a compiler, and examines the kind of compiler infrastructure that will be required to address them. 1 Overview Developments in the design of microprocessors will shape tomorrow's computing systems. Microprocessor-based personal computers and workstations dominate the desktop; today's fastest supercomputers are actually large collections of microprocessors linked together in some regular way. Recent years have seen rapid changes in the design of microprocessors and systems built around them. These developments have shifted a larger share of the burden for achieving a machine's peak performance from the hardware to the software. That is, the programmer and the compiler must take more of the responsibility for achieving high performance on these systems. In their quest for ever higher peak performance, the architects of modern microprocessors have turned to a collection of features that are diicult for conventional compilers to exploit. A typical advanced architecture microprocessor has several pipelined functional units, issues several instructions per cycle, and has a short cycle time relative to its surrounding RAM chips. Independently, multiple pipelines, wide instructions, and relatively slow memories pose challenges to the compiler. Taken together, they present a daunting challenge. (Fortunately, not all of the features in modern microprocessors pose problems. These machines have large register sets, uniform addressing modes, and RISC-style integer units, each of which simpliies some aspect of compilation.) To make interesting systems out of microprocessors, architects embed them inside memory hierarchies. Single level caches are the rule; multiple level caches are beginning to appear. To achieve higher aggregate performance, a group of microprocessors is connected to a private communications network to form a mul-tiprocessor. Memory can be either local to a processor or shared among multiple processors; the extent of sharing varies widely. (One likely side eeect of sixty-four bit addressing is that users will expect to be able to address any byte in the machine, even when the memories are very large.)